Hiring data · updated October 27, 2026
Chip design and verification engineer jobs
There are 431 open chip design and verification engineer roles at 56 of the companies we track, 321 of them in the US. SpaceX, Astera Labs, and Omni Design Technologies have the most openings, and the most roles are in San Francisco Bay Area, Austin, and Bangalore. US postings that list pay have a median range of $168K–$250K a year. 22 are internships or entry-level.
Newest chip design and verification engineer jobs
| Role | Company | Location | Level | Posted |
|---|---|---|---|---|
| Sr. SOC Physical Verification Engineer (Silicon Engineering) | SpaceX | Palo Alto, CA | Senior | Oct 26 |
| PCB Layout Engineer | Lunar Energy | Mountain View, CA | Mid-level | Oct 26 |
| Sr. IC Package Design Engineer (Silicon Engineering) | SpaceX | Austin, TX | Senior | Oct 23 |
| Sr. IC Package Design Engineer (Silicon Engineering) | SpaceX | Irvine, CA | Senior | Oct 23 |
| Advanced SerDes & Analog/Mixed-Signal IC Design Intern – Summer 2027 | Upscale AI | US - Headquarters | Internship | Oct 23 |
| Senior Director, AMS Layout Engineering | Upscale AI | US - Headquarters | Leadership | Oct 22 |
| Principal ASIC Engineer (Mixed-Signal) | Voyant Photonics | New York Office (HQ) | Senior | Oct 22 |
| Hardware Engineer, DFT | Normal Computing | Mountain View | Mid-level | Oct 22 |
| Digital Verification Engineer | Efficient Computer | San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX | Mid-level | Oct 21 |
| RTL Lead | Normal Computing | Mountain View + 1 more | Senior | Oct 21 |
| Senior Silicon Photonics Design Engineer (Remote) | Voyant Photonics | Remote | Senior | Oct 20 |
| Senior Silicon Photonics Design Engineer (Onsite/Hybrid) | Voyant Photonics | New York Office (HQ) / Hybrid | Senior | Oct 20 |
| Physical Design Lead | Normal Computing | Mountain View + 1 more | Senior | Oct 20 |
| Principal Post-Silicon Validation Engineer | Astera Labs | San Jose, California, United States | Senior | Oct 20 |
| Internal Acceleration, Engineer (ASIC) | Etched | San Jose | Mid-level | Oct 15 |
| Sr. Principal Engineer, Scale-Up (Switch Silicon & Traffic Management) | Upscale AI | US - Headquarters | Senior | Oct 15 |
| Director ASIC Technical Program Management | Astera Labs | San Jose, California, United States | Leadership | Oct 15 |
| Senior Digital Verification Engineer - Contract | Efficient Computer | San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX | Senior | Oct 14 |
| Senior RTL Design Engineer | Efficient Computer | San Francisco, Bay Area OR Pittsburgh, PA OR Austin, TX | Senior | Oct 14 |
| SoC Engineer | OpenAI | San Francisco | Mid-level | Oct 14 |
| AMS Design Verification Engineer Intern | Astera Labs | San Jose, CA | Internship | Oct 13 |
| Staff HSIO Digital & Mixed Signal Design Engineer | Samsung | San Jose, California, United States | Senior | Oct 13 |
| Validation & Verification Engineer | Skyryse | El Segundo, CA | Mid-level | Oct 12 |
| Verification Engineer - ADAS Driving & Safety Features | Lucid Motors | Newark, CA | Mid-level | Oct 12 |
| Principal ASIC Verification Engineer | Atom Computing | Austin, TX | Senior | Oct 8 |
| Director - Post-Silicon Validation (Functional) | Graphcore | Austin, Texas, United States | Leadership | Oct 8 |
| Senior ASIC RTL Design Engineer, AI Hardware | Cerebras | Sunnyvale, CA | Senior | Oct 7 |
| Hardware Intern - Architecture, AI HW & SoC (USA) | Tenstorrent | Austin, Texas, United States; Boston, Massachusetts, United States; Fort Collins | Internship | Oct 7 |
| Silicon Intern - Physical Design & DFT (USA) | Tenstorrent | Austin, Texas, United States; Boston, Massachusetts, United States; Fort Collins | Internship | Oct 7 |
| Silicon Qubit Development Lead | HRL Laboratories | Malibu, CA | Senior | Oct 6 |
The newest postings, at most three per company. Each links to the company's own job board.
Who's hiring the most
| SpaceX | 77 | 18% | |
| Astera Labs | 75 | 17% | |
| Omni Design Technologies | 28 | 6% | |
| Etched | 23 | 5% | |
| Graphcore | 22 | 5% | |
| K2 Space | 22 | 5% | |
| Lightmatter | 16 | 4% | |
| Samsung | 13 | 3% | |
| Eliyan | 12 | 3% | |
| Voyant Photonics | 11 | 3% | |
| Efficient Computer | 10 | 2% | |
| Upscale AI | 9 | 2% |
Where the jobs are
| San Francisco Bay Area | 176 | 41% | |
| Austin | 60 | 14% | |
| Bangalore | 42 | 10% | |
| Orange County | 23 | 5% | |
| Seattle | 22 | 5% | |
| New York City | 19 | 4% | |
| Toronto | 18 | 4% | |
| Tel Aviv | 15 | 3% | |
| Los Angeles | 13 | 3% | |
| Boston | 12 | 3% | |
| Pittsburgh | 10 | 2% | |
| Hyderabad | 10 | 2% |
Chip design and verification engineer pay
| Level | Median posted range | Postings with pay |
|---|---|---|
| Mid-level | $150K–$216K | 85 |
| Senior | $175K–$260K | 133 |
Medians of the low and high ends of the pay ranges stated in US postings. Where most postings give an hourly rate it's shown per hour; otherwise per year, with hourly rates annualized at 2,080 hours. Bonuses and equity aren't included.
Seniority
| Internship | 21 | 5% | |
| Entry-level | 1 | 0% | |
| Mid-level | 154 | 36% | |
| Senior | 238 | 55% | |
| Leadership | 17 | 4% |
21 chip design and verification engineer internships →
Majors that lead here
Thinking about a degree for this path? See what these majors earn, cost and lead to:
Related roles
Questions
How many chip design and verification engineer jobs are open right now?
431 at 56 companies on October 27, 2026, 27 posted in the previous 7 days. This page is refreshed every Monday.
Which companies are hiring the most for chip design and verification engineer jobs?
SpaceX (77), Astera Labs (75), Omni Design Technologies (28), Etched (23), and Graphcore (22).
How much do chip design and verification engineer jobs pay?
Across 225 US postings that state pay, the median range is $168K–$250K a year; the middle half of ranges runs from about $140K to $280K. By level: mid-level $150K–$216K, senior $175K–$260K.
Can chip design and verification engineer jobs be remote?
7% of US chip design and verification engineer jobs on our list are listed as remote (24 of 321).
Looking for chip design and verification engineer roles?
Lil Sally applies to internships and entry-level roles for you overnight, straight on the company’s own job board, and tells you what she sent in the morning.
About this data
We read the public job boards (Greenhouse, Lever and Ashby) of the companies on our list every Monday; this page uses the October 27, 2026 read. Roles are grouped from job titles, so some titles land in the wrong bucket. ElegyLabs isn't affiliated with the companies listed; we link to each posting on the company's own board and don't copy job descriptions. Pay figures are the ranges stated in the postings.
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